1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor apparatus and related methods. In particular, certain embodiments relate to a test mode control circuit of a semiconductor apparatus and a control method thereof.
2. Related Art
In a semiconductor apparatus, circuit blocks which are used inside the semiconductor apparatus are tested using test modes, and corresponding test results are stored, so that the circuit blocks are operated in conformity with the stored test results in a normal mode.
Referring to FIG. 1, a conventional test mode control circuit 1 of a semiconductor apparatus may include a test mode control block 10, a plurality of fuse sets 20, and global lines 40.
The test mode control block 10 is configured to generate test mode signals according to external commands and address signals.
In the conventional art, when generating the test mode signals, address signals of 7 bits may be used. That is, a maximum of 128 test mode signals may be generated.
The plurality of fuse sets 20 are connected in one-to-one correspondence with circuit blocks (e.g., use logics ULs) 30 which operate inside the semiconductor apparatus.
The plurality of fuse sets 20 are used to store information as to whether or not to use test modes. For example, the plurality of fuse sets 20 may be configured to store test mode signals and transfer, in a normal operation mode, the stored test mode signals to the circuit blocks (ULs) 30 which are connected with the fuse sets 20.
Since the fuse sets 20 and the circuit blocks (ULs) 30 correspond one-to-one with each other, the global lines 40 for transferring the test mode signals generated by the test mode control block 10 should be provided as many as the number of the test mode signals.
The plurality of circuit blocks 30 shown in FIG. 1 may be included in memory banks BANK A through BANK H shown in FIG. 2.
The global lines 40 are disposed entirely over a peripheral region PERI, and the fuse sets 20 are evenly disposed over the peripheral region PERI adjacent to the memory banks BANK A through BANK H.
The conventional art described above may have the following problems.
First, since the test mode signals are generated by the combinations of the 7-bit address signals, the number of test modes to be generated is limited to 128 at the maximum.
Second, since the fuse sets 20 and the circuit blocks (ULs) 30 correspond one-to-one with each other, a large number of fuse sets are needed. Further, since as many global lines 40 as the number of the test mode signals are needed, a circuit area may be increased.